? semiconductor components industries, llc, 2011 september, 2011 ? rev. 0 1 publication order number: NVD5117PL/d NVD5117PL power mosfet ? 60 v, 16 m , ? 61 a, single p ? channel features ? low r ds(on) to minimize conduction losses ? high current capability ? avalanche energy specified ? aec ? q101 qualified ? these devices are pb ? free, halogen free/bfr free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss ? 60 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r jc (note 1) steady state t c = 25 c i d ? 61 a t c = 100 c ? 43 power dissipation r jc (note 1) t c = 25 c p d 118 w t c = 100 c 59 continuous drain cur- rent r ja (notes 1 & 2) steady state t a = 25 c i d ? 11 a t a = 100 c ? 8 power dissipation r ja (notes 1 & 2) t a = 25 c p d 4.1 w t a = 100 c 2.1 pulsed drain current t a = 25 c, t p = 10 s i dm ? 419 a current limited by package (note 3) t a = 25 c i dmaxpkg 60 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s ? 11 8 a single pulse drain ? to ? source avalanche energy (t j = 25 c, v dd = 50 v, v gs = 10 v, i l(pk) = 40 a, l = 0.3 mh, r g = 25 ) e as 240 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance maximum ratings parameter symbol value unit junction ? to ? case ? steady state (drain) r jc 1.3 c/w junction ? to ? ambient ? steady state (note 2) r ja 37 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 3. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. dpak case 369c style 2 marking diagrams & pin assignment ? 60 v 16 m @ ? 10 v r ds(on) ? 61 a i d v (br)dss 22 m @ ? 4.5 v http://onsemi.com 1 2 3 4 p ? channel d s g 1 gate 2 drain 3 source 4 drain yww 51 17lg y = year ww = work week 5117l = device code g = pb ? free package device package shipping ? ordering information NVD5117PLt4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
NVD5117PL http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = ? 250 a ? 60 v zero gate voltage drain current i dss v gs = 0 v, v ds = ? 60 v t j = 25 c ? 1.0 a t j = 125 c ? 100 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = ? 250 a ? 1.5 ? 2.5 v drain ? to ? source on resistance r ds(on) v gs = ? 10 v, i d = ? 29 a 12 16 m v gs = ? 4.5 v, i d = ? 29 a 16 22 froward transconductance g fs v ds = ? 15 v, i d = ? 15 a 30 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = ? 25 v 4800 pf output capacitance c oss 480 reverse transfer capacitance c rss 320 total gate charge q g(tot) v ds = ? 48 v, i d = ? 29 a v gs = ? 4.5 v 49 nc v gs = ? 10 v 85 threshold gate charge q g(th) v gs = ? 4.5 v, v ds = ? 48 v, i d = ? 29 a 3 gate ? to ? source charge q gs 13 gate ? to ? drain charge q gd 28 plateau voltage v gp 3.2 v switching characteristics (notes 4) turn ? on delay time t d(on) v gs = ? 4.5 v, v ds = ? 48 v, i d = ? 29 a, r g = 2.5 22 ns rise time t r 195 turn ? off delay time t d(off) 50 fall time t f 132 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = ? 29 a t j = 25 c ? 0.86 ? 1.0 v t j = 125 c ? 0.74 reverse recovery time t rr v gs = 0 v, dl s /dt = 100 a/ s, i s = ? 29 a 36 ns charge time t a 19 discharge time t b 17 reverse recovery charge q rr 44 nc 4. pulse test: pulse width 300 s, duty cycle 2%.
NVD5117PL http://onsemi.com 3 typical characteristics 0 20 40 60 80 100 120 012345 figure 1. on ? region characteristics ? v ds , drain ? to ? source voltage (v) ? i d , drain current (a) ? 4.5 v v gs = ? 10 v t j = 25 c ? 4.2 v ? 4 v ? 3.8 v ? 3.6 v ? 3.4 v ? 3.2 v ? 3 v 0 20 40 60 80 100 120 23456 figure 2. transfer characteristics ? v gs , gate ? to ? source voltage (v) ? i d , drain current (a) v ds ? 10 v t j = 25 c t j = ? 55 c t j = 125 c figure 3. on ? resistance vs. gate ? to ? source voltage ? v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) 0.010 0.012 0.014 0.016 0.018 0.020 0.022 0.024 10 20 30 40 50 60 70 80 90 100 110 120 figure 4. on ? resistance vs. drain current and gate voltage ? i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) v gs = ? 4.5 v t j = 25 c v gs = ? 10 v 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 ? 50 ? 25 0 25 50 75 100 125 150 175 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) r ds(on) , drain ? to ? source resistance (normalized) v gs = ? 10 v i d = ? 29 a 100 1000 10000 100000 figure 6. drain ? to ? source leakage current vs. voltage ? v ds , drain ? to ? source voltage (v) ? i dss , leakage (na) t j = 125 c t j = 150 c 0.005 0.015 0.025 0.035 0.045 0.055 0.065 345678910 i d = ? 29 a t j = 25 c 5 1015202530354045505560 v gs = 0 v
NVD5117PL http://onsemi.com 4 typical characteristics figure 7. capacitance variation ? v ds , drain ? to ? source voltage (v) c, capacitance (pf) c iss c oss c rss v gs = 0 v t j = 25 c 0 2 4 6 8 10 0 102030405060708090 figure 8. gate ? to ? source vs. total charge q g , total gate charge (nc) ? v gs , gate ? to ? source voltage (v) q t q gs q gd v ds = ? 48 v i d = ? 29 a t j = 25 c 1.0 10.0 100.0 1000.0 110100 figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( ) t, time (ns) v dd = ? 48 v i d = ? 29 a v gs = ? 10 v t d(off) t d(on) t r t f 0 20 40 60 80 100 120 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 figure 10. diode forward voltage vs. current ? v sd , source ? to ? drain voltage (v) i s , source current (a) t j = 25 c v gs = 0 v figure 11. maximum rated forward biased safe operating area ? v ds , drain ? to ? source voltage (v) ? i d , drain current (a) v gs = ? 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 10 s 1 ms dc 10 ms 0 50 100 150 200 250 25 50 75 100 125 150 175 figure 12. maximum avalanche energy vs. starting junction temperature t j , starting junction temperature ( c) e as , single pulse drain ? to ? source avalanche energy (mj) i d = ? 40 a 0.1 1 10 100 1000 0.1 1 10 100 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 0 102030405060
NVD5117PL http://onsemi.com 5 typical characteristics 0.01 0.1 1 10 0.000001 0.00001 0.0001 0.001 0.01 0.1 figure 13. thermal response pulse time (sec) r jc(t) ( c/w) effective transient thermal resistance 0.1 duty cycle = 0.5 0.2 0.05 0.02 0.01 single pulse
NVD5117PL http://onsemi.com 6 package dimensions dpak (single gauge) case 369c ? 01 issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NVD5117PL/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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